SiGeC Cantilever Micro Cooler

The fabrication and characterization of SiGeC cantilever microcoolers are described. Silicon on insulator (SOI) was used as the substrate, and two layers of 3 μm p-SiGe0.07C0.0075 and 1.14 μm n-SiGe0.07C0.0075 lattice matched to silicon were grown using molecular beam epitaxy. The uni couple cooler was fabricated using conventional integrated circuit (IC) processing, and the cantilever structure was finally formed by removing the backside Si of SOI substrate by deep reactive ion etching. Devices with different nand p-side length ratios were characterized. Cooling by 1.2K has been measured at room temperature. Modeling showed that the device performance was dominated by the smaller cooling temperature of the p-SiGeC leg of the cantilever structure. Parasitic heat conduction through the Si buffer layer is the main limitation to the device performance.